5GHz, 4-Channel MIMO Transmitter
8 ______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICSTIMING (continued)
(Operating conditions, unless otherwise specified: V
CC
= 2.7V~3.6V, frequency = 5.35GHz, T
A
= -25NC to +85NC,. Reference fre-
quency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, typical values measured at V
CC
= 2.85V, LO frequency = 5.35GHz,
T
A
= +25NC.) (Note 1)
Note 1: The MAX2850 is production tested at T
A
= +25NC; minimum/maximum limits at T
A
= +25NC are guaranteed by test, unless
specified otherwise. Minimum/maximum limits at T
A
= -25NC and +85NC are guaranteed by design and characterization.
There is no power-on register settings self-reset; recommended register settings must be loaded after V
CC
is applied.
Note 2: For optimal Rx and Tx quadrature accuracy over temperature, the user can utilize the Rx calibration and Tx calibration
circuit to assist quadrature calibration.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rx/Tx Turnaround Time
Measured
from CS ris-
ing edge
Rx to Tx mode, Tx gain settles
to within 0.2dB of steady state
2
Fs
Tx to Rx mode with RXHP = 1,
Rx gain settles to within 0.5dB
of steady state
2
Tx Turn-On Time (from
Standby Mode)
Measured from CS rising edge, Tx gain settles
to within 0.2dB of steady state
2
Fs
Tx Turn-Off Time (to Standby
Mode)
From CS rising edge
0.1
Fs
Rx Turn-On Time (from
Standby Mode)
Measured from CS rising edge, Rx gain settles
to within 0.5dB of steady state
2
Fs
Rx Turn-Off Time (to Standby
Mode)
From CS rising edge
0.1
Fs
4-WIRE SERIAL-INTERFACE TIMING (See Figure 1)
SCLK Rising Edge to CS
Falling Edge Wait Time
t
CSO
6
ns
Falling Edge of CS to Rising
Edge of First SCLK Time
t
CSS
6
ns
DIN to SCLK Setup Time
t
DS
6
ns
DIN to SCLK Hold Time
t
DH
6
ns
SCLK Pulse-Width High
t
CH
6
ns
SCLK Pulse-Width Low
t
CL
6
ns
Last Rising Edge of SCLK to
Rising Edge of CS or Clock to
Load Enable Setup Time
t
CSH
6
ns
CS High Pulse Width
t
CSW
50
ns
Time Between Rising Edge of
CS and the Next Rising Edge
of SCLK
t
CS1
6
ns
SCLK Frequency
f
CLK
40
MHz
Rise Time
t
R
2.5
ns
Fall Time
t
F
2.5
ns
SCLK Falling Edge to Valid
DOUT
t
D
12.5
ns
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